Embodiments of the invention relate generally to structures and methods for packaging semiconductor devices and, more particularly, to an ultra-thin power device packaging structure having power overlay (POL) interconnects that form all electrical and thermal interconnections in the structure, with the packaging structure having reduced inductance.
Power semiconductor devices are semiconductor devices used as switches or rectifiers in power electronic circuits, such as switched mode power supplies, for example. In use, power semiconductor devices are typically surface mounted to an external circuit by way of a packaging structure, with the packaging structure providing an electrical connection to the external circuit and also providing a way to remove the heat generated by the devices and protect the devices from the external environment. Alternatively, especially for higher power ranges, the power modules packaging structures may have large terminals for connection to the external circuit which add significant inductance and increase the size of the module.
Most existing power device packaging structures use wirebonds, a multi-layer substrate (e.g., a direct bond copper (DBC) substrate), and are leaded (leadframe, etc.) or provided with bolted terminals for providing electrical and thermal connectivity to the packaging structure. The wirebonds make the connections from one surface of the packaging structure to package pins, which then interface to the external circuit, with a DBC being connected to the other surface of the packaging structure (e.g., soldered thereto). It is recognized, however, that the DBC adds significant cost to the packaging structure both from a materials standpoint and from a processing standpoint—as additional processing steps and temperature excursions are required when including a DBC in the packaging structure, such as soldering and flux cleaning processes required for joining the DBC to the packaging structure. It is also recognized that the wirebonds and leads add significant parasitic inductance that reduces the efficiency of the package. Wirebonds also add significant height to the package. It is still further recognized that—while the leads on the packaging structure allow higher thermal cycling reliability and are not subject to stringent Moisture Sensitivity Level (MSL) Requirements—the leads or terminals in a power module can be quite large and affect the module foot-print and thickness on the PCB and also negatively impact the electrical performance due to high inductance.
Therefore, it would be desirable to provide a semiconductor device package structure that eliminates the need for a multi-layer DBC or PCB substrate and wirebond connections, so as to provide a very thin package structure with ultra low inductance. It would further be desirable for such a package structure to have a high device density and a small foot-print, so as to enable system miniaturization to improve electrical and reliability performance of the package.